Two semiconductor wafers, dies, and/or other substrates may be assembled utilizing through-silicon vias (TSVs) that extend through the thickness of the substrate. The top surface of at least one of the substrates comprises circuitry formed therein and/or thereon, whereas bond pads and a redistribution layer (RDL) are formed on the bottom surface to distribute power and signals to the circuitry through the TSVs.
A conventional RDL may comprise copper with an ENEPIG (electroless nickel—electroless palladium—immersion gold) surface finish. However, as such processing became quite expensive, a proposed alternative entailed incorporating an RDL comprising aluminum instead of copper. Nonetheless, shortcomings also exist with this alternative.
For example, the patterning utilized in forming an RDL comprising aluminum requires additional processes to generate alignment marks utilized during lithography, such as to ensure a certain step height after the TSV formation for alignment marks. However, this step height introduces seam issues in the aluminum film, such as may be attributable to poor step coverage attainable with physical-vapor deposition (PVD) of the aluminum film.